1. Field of the Invention
The present invention relates to a reversible energy recovery logic circuit, and more particularly, to a reversible adiabatic logic circuit for eliminating non-adiabatic energy loss using a pair of PMOS transistors cross-coupled to an NMOS transistor network, and a pipelined reversible adiabatic logic apparatus employing the same.
2. Description of the Related Art
Adiabatic charging circuits have been steadily studied for attaining low-power consumption MOS logic circuits since they were proposed. In charging a voltage of a node in a standard CMOS logic circuit, assuming that a potential difference between both ends of switch is referred to as V.sub.dd, power of (1/2)C.sub.L V.sub.dd.sup.2 is consumed by switch resistance until the node (having capacitance C.sub.L) is completely charged when the switch (e.g., a MOSFET) connected to the power supply is turned off. However, if the voltage of the node becomes equal to the power supply voltage, even if the power supply is connected to the node by the switch, current does not flow into the switch, thereby avoiding power consumption due to the switch resistance.
Therefore, if the power supply voltage is increased relatively slowly, compared to a time constant RC.sub.L between the switch resistance R and the node capacitance C.sub.L, the node voltage can be increased to be substantially equal to the power supply voltage while reducing a potential difference between both ends of the switch. Then, the node voltage is conformed to the power supply voltage, thereby adiabatically charging the capacitance of the node. Here, the power dissipated by the switch resistance is represented as: EQU E=I.sup.2 RT=(C.sub.L V.sub.dd /T).sup.2 RT=(2RC.sub.L /T)(1/2C.sub.L V.sub.dd.sup.2) Equation (1)
wherein T denotes a time period for charging. Here, if T is infinitive, the power needed for charging the capacitance C.sub.L of the node can be made zero. This charging method is called an adiabatic charging method, which is markedly different from the standard charging method of a CMOS circuit free of the time constant RC.sub.L in context of dissipating energy.
In a CMOS inverter shown in FIG. 1, for example, if an input V.sub.IN applied to an input node N1 changes in such a manner as shown in FIG. 2A, an output V.sub.OUT of an output node N2 changes in such a manner as shown in FIG. 2B. In other words, if the input V.sub.IN ramps down from a high level to a low level at a timing t1, a PMOS transistor Q1 is turned on and an NMOS transistor Q2 is turned off, so that the output node N2 is charged up to the power supply voltage V.sub.dd by charging current I1, through the PMOS transistor Q1.
Conversely, if the input V.sub.IN ramps up from a low level to a high level at a timing t2, the PMOS transistor Q1 is turned off and the NMOS transistor Q2 is turned on, so that the output node N2 is discharged to a power supply line 2 by discharging current 12, through the NMOS transistor Q2.
Therefore, in the conventional charging method, as shown in FIG. 3, a potential difference V1 between the constant power supply voltage V.sub.dd, i.e., .alpha.1, and the voltage .alpha.2 of the output node N2, may cause a switching loss. In this regard, according to the above adiabatic charging method, since the power supply voltage V.sub.dd changes as indicated by symbol .alpha.3, and the voltage of the output node N2 also changes as indicated by symbol .alpha.4 in response to the change of the power supply voltage V.sub.dd, the loss caused thereby is reduced to a small amount corresponding to a potential difference indicated by symbol V2.
Recently, MOS transistor circuits using the above-described adiabatic charging method have been actively studied. For example, ECRL (Efficient Charge Recovery Logic) using the adiabatic charging method or dual-rail adiabatic logic circuit called a 2N-2N2P circuit has been proposed in publications by Y. Moon and D. K. Jeong, entitled "An Efficient Charge Recovery Logic Circuit," IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, 1996, pp. 514-522, and by A. Kramer, J. Denker and J. Moroney, entitled "2.sup.nd Order Adabatic Computation with 2N-2P and 2N-2N2P Logic Circuits," International Symposium on Low Power Design, 1995, pp. 191-196.
However, these adiabatic logic circuits are associated with a non-adiabatic loss in addition to the adiabatic loss expressed in Equation (1). In the case of the 2N-2N2P circuits and ECRL circuits, the non-adiabatic loss is generated by a potential difference between both ends of a switch during a switching operation. In other words, in the 2N-2N2P circuits, an energy loss corresponding to C.sub.L V.sub.dd V.sub.th is generated by a diode used for precharging of the circuits. In the ECRL circuits, an energy loss corresponding to (1/2)C.sub.L V.sub.th.sup.2 is generated by threshold voltages (V.sub.th) of MOS transistors.
In order to avoid the non-adiabatic energy loss, the following two requirements must be satisfied. First, only when there is no potential difference between both ends of a switch (e.g., MOSFET), the switch must be turned on. When the switch is turned on in the presence of a potential difference between both ends thereof, an abrupt change in the voltage makes a large amount of current flow in the switch due to resistance present therein, thereby generating heat, which implies an energy loss. Second, once the switch is turned on, the energy must be slowly transferred so that a potential difference may not produced at both ends of the switch. The above-described adiabatic charging method has been proposed for satisfying these two requirements.
In order to supply the energy of a node and restore the same while satisfying the two requirements, it is necessary to know the state (or voltage) of the node, which can be solved by using reversible logic. The reversible logic is capable of reverse computation and allows the energy of an input stage to be restored by deriving an input value from an output value through a reverse logic function circuit. Therefore, the reversible logic can be used for restoration of energy.
One approach to low-power circuits using the reversible logic concept is reversible computer technology. Research into reversible computer systems aims at developing computers in which energy or power dissipation is very low. This is based on a physical theory asserting that no data loss leads to avoidance of energy loss, and those computers are promising next-generation computer models which can solve problems of heat and life. The important fields to which the reversible computer technology can be applied include a transplantation field of artificial internal organs, which requires extremely small power consumption. According to physical theories, computers can be designed so as not to consume energy if only reversible computation is allowed. Thus, reversible computers must be implemented using, reversible logic for reversible computation. However, most of conventional computation logic systems are irreversible. Thus, many approaches for converting the irreversible logic system into reversible ones have been disclosed. Existing Boolean functions which are mostly irreversible must be converted into reversible logic systems for being used, which may, however, cause an increase in the complexity. However, the complexity problem can be expected to overcome by the development of high-level integration technology. Ultimately, in view of minimization of energy dissipation, implementation of reversible logic circuits is a very important approach.
Logic elements and apparatuses for reducing energy dissipation using the above-described reversible logic and adiabatic charging method, have been disclosed in an article proposed by S. G. Younis and T. Knight, entitled "Asympotically Zero Energy Split-Level Charge Recovery Logic," Workshop on Low Power Design, 1994, pp. 177-182, and an article proposed by W. C. Athas, L. Swensson, J. G. Koller, N. Tzartzanis and E. Y. -C. Chou, entitled "Low Power Digital Systems Based on Adiabatic Switching Principles," IEEE Trans, on VLSI Systems, 1994, pp. 398-407.
FIGS. 4 through 7 show a logic circuit disclosed by Athas et al. FIG. 4 shows irreversible pipeline connection, in which thick arrows indicate charging/discharging paths or directions. FIG. 5 partially shows the pipelined reversible structure shown in FIG. 4, illustrating an exemplary implementation of a buffer using transmission gates. FIG. 6 is a timing diagram of power clocks used in FIGS. 4 and 5, in which the power clocks have 8 phases and neighboring clocks have a phase difference of at least 1/8 a time period. FIG. 7 is a waveform diagram for illustrating the operation of various nodes. FIG. 8 briefly shows an exemplary implementation of a logic function computing unit and a complementary logic function computing unit, for obtaining the sum (S=a XOR b XOR C.sub.in) of a full adder in FIG. 5, in which a switch and a clamping circuit are not shown.
In FIG. 5, a switch implemented by transmission gates is in a positive logic level. Thus, a complementary dual rail circuit for receiving two complementary inputs and computing two complementary outputs is used for generating a negative logic value. One rail of the circuit computes an output value of a positive logic level, and the other rail thereof computes an output value of a negative logic level, the two output values to be used as inputs of the next stage. In the complementary dual rail circuit, since one rail is turned off, it may be affected by capacitive coupling in a chip. To overcome this problem, a clamping circuit 15 is provided. The clamping circuit 15 consists of two NMOS transistors M9 and M10, and forces one rail to be coupled to a ground port while the other rail is turned on.
However, in the logic circuit shown in FIGS. 4 and 5, an identical clock is used as charging and discharging clocks in computing logic functions. For example, in a first-stage forward logic function circuit F and a second-stage reverse logic function circuit G.sup.-1, an identical clock .phi..sub.0 is used as charging and discharging clocks. Thus, non-adiabatic energy dissipation is caused, which will now be described in detail with reference to FIGS. 5 to 7.
First, it is assumed that internal nodes n1, n2, n3 and n4 are grounded at an initial stage, and two switches T5 and T6 are turned on. When T=0, an input .alpha..sub.0 is valid to a logic high level. When T=1, an output node X.sub.1 is driven to a logic high level, and its complementary output node /X.sub.1 is grounded by the clamping circuit 15. Simultaneously, as the PMOS transistor (not shown) of transmission gates T3 and T4 are turned on, the nodes n3 and n4 are charged. Here, since inputs .beta..sub.2 and /.beta..sub.2 are at an idle state when T=1, they are kept being grounded. When T=3, a clock .phi.3 goes high and switches T7 and T8 are turned on. Then, the charged node n4 is connected to the grounded node /X.sub.1 so that the non-adiabatic loss as indicated by a circle "A" in FIG. 7 is generated. When T=4, the inputs .alpha..sub.0 and /.alpha..sub.0 goes to an idle state so that the discharged node n2 is connected to the clock .phi..sub.3 being at a high level. Accordingly, the non adiabatic loss as indicated by a circle "B" in FIG. 7 is generated.
Referring to FIG. 5, in the forward logic function circuit or reverse logic function circuit 11 or 13 including two switches T5 and T6 or T7 and T8, respectively, the logic circuits for computing a forward logic function, a reverse logic function and their complementary logic functions are implemented using transmission gates. The transmission gates are driven such that the source of the NMOS transistor and the drain of the PMOS transistor are connected to each other, the source and drain being used as both ends of a switch, the input is connected to the gate of the NMOS transistor, and its complementary input is connected to the gate of the PMOS transistor. Then, energy is transferred to both ends of the switch without a voltage drop. The transmission gate is known as the most stable switch that is implemented by MOS transistors. However, since the transmission gates are implemented using a pair of NMOS and PMOS transistors, the circuitry becomes bulky and energy dissipation increases.